A FinFET-Based Low Leakage 10T Static Random Access Memory Cell.

In this work, a transmission gate-based low-power ten FinFET (TGLP10T) single-ended read/write SRAM cell is proposed. The proposed cell achieves low leakage operation along with improved write-ability. The performance metric results obtained from TGLP10T are compared with five previously published bit-cell designs, i.e., conventional 6T (Con6T), robust transmission gate-based 10T SRAM (RTG10T), transmission gate-based variation resistant 9T SRAM (TGVR9T), PNN (PMOS-NMOS-NMOS) inverter-based 10T (PNN10T) and PPN (PMOS-PMOS-NMOS) inverter-based read decoupled 10T (PPNRD10T. The leakage power in proposed design is reduced by 1. 2 7 × ∕ 1. 1 5 × ∕ 1. 3 3 × ∕ 1. 1 5 × ∕ 1. 0 0 × compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The write power and WSNM are improved by 1. 0 7 × ∕ 1. 4 0 × ∕ 0. 8 7 × ∕ 1. 6 3 × ∕ 0. 7 8 × and 1. 5 7 × ∕ 1. 6 9 × ∕ 1. 0 8 × ∕ 1. 5 9 × ∕ 1. 5 0 × ∕ 1. 0 0 × , respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The read delay and write delay are improved by 1. 0 0 × ∕ 1. 5 4 × ∕ 1. 3 6 × ∕ 1 × ∕ 2. 8 3 × and 1.68 × ∕ 2. 3 5 × ∕ 1. 8 2 × ∕ 2. 8 9 × ∕ 1. 7 7 × , respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The proposed design shows the least data retention voltage compared to other SRAM bit-cells. [ABSTRACT FROM AUTHOR]