Design and Evaluation of a New Nanoscale and Cost-Efficient Coplanar Digital Parity Generator Based on Quantum Dots.

A parity generator as a combinational logic circuit in digital circuits can generate the parity bit in the transmitter. It is very applicable in digital networking and communications. Also, rather than diodes and transistors, quantum dots will be used in the next-generation circuits. Quantum-dot Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits' functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively. Quantum dot-Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits' functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively. [ABSTRACT FROM AUTHOR]