NUMA-aware parallel sparse LU factorization for SPICE-based circuit simulators on ARM multi-core processors.

The article focuses on the development and evaluation of HLU, a parallel sparse direct solver designed to improve the performance of sparse lower-upper (LU) factorization in circuit simulators resembling the Simulation Program with Integrated Circuit Emphasis (SPICE). HLU introduces a fine-grained scheduling method based on an elimination tree in pipeline mode to maximize task-level parallelism and reduce thread waiting time, alongside two NUMA (non-uniform memory access) node affinity strategies for optimized thread mapping and memory placement on multi-NUMA systems. Experimental results on Huawei Kunpeng 920 and Intel Xeon Gold 5120 servers demonstrate that HLU achieves significant speedups—up to 9.14× over KLU and 1.26× over NICSLU (both established sparse solvers) on circuit simulation matrices—and also shows improved performance on general sparse matrices. The solver addresses challenges related to the irregular sparsity and strong data dependencies of circuit matrices, ARM architecture memory consistency, and NUMA system memory access latency, making it applicable to both circuit simulation and broader scientific computing domains.