Erratum: Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications.

This erratum addresses a correction to the corresponding author information for the article titled "Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications," originally published in 2023. The corresponding author has been updated from M. Elangovan of the Government College of Engineering, Srirangam, Tamilnadu, India, to A. Venkatesan of Kingston Engineering College, Vellore, Tamilnadu, India. The article focuses on a low power-delay product (PDP) adiabatic full adder design using 7nm FINFET technology intended for multiple-input multiple-output (MIMO) applications.