Theoretical Investigation of Dual-Material Stacked Gate Oxide-Source Dielectric Pocket TFET Based on Interface Trap Charges and Temperature Variations.

In this paper, the performance of dual-material stacked gate oxide-source dielectric pocket-tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed interface trap charges (ITCs) at the Si–SiO2 interface. During the analysis, both types of trap charges, positive (donor) and negative (acceptor), have been considered to investigate their effect on the DC, analog/ radio frequency, linearity and harmonic distortion performance parameters in terms of the carrier concentration, electric field, band-to-band tunneling rate, transfer characteristics, transconductance ( g m ), unity gain frequency ( f T ), gain–bandwidth product, device efficiency ( g m / I DS ), transconductance frequency product, transit time (τ), second- and third-order transconductance and voltage intercept points ( g m 2 , g m 3 , VIP2 and VIP3), third-order Input Intercept Point and Intermodulation Distortion (IIP3, IMD3), second-, third-order and total harmonic distortions (HD2, HD3 and THD), respectively. Further, the impact of temperature variations from 2 0 0 K to 5 0 0 K in the presence of ITCs is investigated and the results are compared with conventional DMSGO-TFET. In terms of percentage variation, DMSGO-SDP-TFET depicts lower variation than conventional DMSGO-TFET, indicating that the proposed device is more immune to trap charges and can be used for energy-efficient, high-frequency and linearity applications at elevated temperatures. [ABSTRACT FROM AUTHOR]